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| HM629127H Series 131072-word x 9-bit High Speed CMOS Static RAM Description The HM629127H is an asynchronous high speed static RAM organized as 131,072-word x 9-bit. It realizes high speed access time (20/25 ns) with employing 0.8 m CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM629127H is packaged in 400-mil 32/36-pin SOJ for high density surface mounting. Features * Single 5 V supply: 5 V 10% * Access time 20/25 ns (max) * Completely static memory No clock or timing strobe required * Equal access and cycle times * Directly TTL compatible All inputs and outputs * 400-mil 36-pin SOJ package * Center VCC and VSS type pinout Ordering Information Type No. HM629127HJP-20 HM629127HJP-25 HM629127HLJP-20 HM629127HLJP-25 Access Time 20 ns 25 ns 20 ns 25 ns Package 400-mil 36-pin Plastic SOJ (CP-36D) HM629127H Series HM629127H Series NC A3 A2 A1 A0 CS I/O1 I/O2 VCC VSS I/O3 I/O4 WE A16 A15 A14 A13 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 (Top View) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 A4 A5 A6 A7 OE I/O9 I/O8 I/O7 VSS VCC I/O6 I/O5 A8 A9 A10 A11 A12 NC Pin Description Pin name A0 - A16 I/O1 - I/O9 CS WE OE VCC VSS NC Function Address Data input/output Chip select Write enable Output enable Power supply Ground No connection 2 HM629127H Series Block Diagram A4 A3 A2 A1 A0 A7 A6 A5 VCC Row Decoder Memory Matrix 256 rows x 512 x 9 columns VSS CS I/O1 . . . I/O9 Column I/O Input Data Control Column Decoder CS A13 A12 A11 A16 A15 A14 A10 A9 A8 WE CS OE CS Absolute Maximum Ratings Parameter Supply voltage relative to VSS Voltage on any pin relative to V SS Power dissipation Operating temperature Storage temperature Storage temperature under bias Symbol VCC VT PT Topr Tstg Tbias Value -0.5 to +7.0 -0.5 *2 *1 Unit V V W C C C to V CC + 0.5 *3 1.0 / 1.5 0 to +70 -55 to +125 -10 to +85 Notes: 1. -2.5 V for pulse width (under shoot) 10 ns 2. at still air condition 3. at air flow 1.0 m/s 3 HM629127H Series Function Table CS H L L L OE X H L X WE X H H L VCC Current I SB , I SB1 I CC I CC I CC I/O High-Z High-Z Output Input Ref. Cycle -- Read cycle Write cycle Note: X: H or L Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage *2 Symbol VCC VSS Min 4.5 0 2.2 -0.5 *1 Typ 5.0 0 -- -- Max 5.5 0 VCC + 0.5 0.8 Unit V V V V Input voltage VIH VIL Notes: 1. -2.0 V for pulse width (under shoot) 10 ns 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 4 HM629127H Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) Parameter Input leakage current Output leakage current Operating power supply current Symbol Min Typ*1 |ILI| |ILO | I CC -- -- -- -- -- 130 Max 2 2 180 Unit A A mA Test Conditions Vin = VSS to V CC VI/O = VSS to V CC 20 ns cycle CS = VIL, Iout = 0 mA Other inputs = VIH/V IL CS = VIH, Other inputs = VIH/V IL Note -- Standby power supply current I SB -- 100 50 160 90 mA mA 25 ns cycle 20 ns cycle -- Standby power supply current (1) I SB1 -- 40 -- 85 2 mA mA 25 ns cycle VCC CS V CC - 0.2 V, 0 V Vin 0.2 V or VCC Vin V CC - 0.2 V L-version I OL = 8 mA I OH = -4 mA -- Output voltage VOL VOH Note: -- 2.4 -- -- -- 0.2 0.4 -- mA V V 1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed. Capacitance (Ta = 25C, f = 1.0 MHz)*1 Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min -- -- Typ -- -- Max 6 8 Unit pF pF Test Conditions Vin = 0 V VI/O = 0 V 1. This parameter is sampled and not 100% tested. 5 HM629127H Series AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted.) Test Conditions * * * * Input pulse levels: VSS to 3.0 V Input rise and fall time: 3 ns Input and output timing reference levels: 1.5 V Output load: See figures +5 V +5 V 480 Dout 255 30 pF*1 Dout 255 480 5 pF*1 Output load (A) Note: 1. Including scope and jig Output load (B) (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW) Read Cycle HM629127H -20 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Symbol t RC t AA t ACS t OE Min 20 -- -- -- 5 3 1 -- -- Max -- 20 20 10 -- -- -- 7 7 -25 Min 25 -- -- -- 5 3 1 -- -- Max -- 25 25 12 -- -- -- 7 7 Unit Note ns ns ns ns ns ns ns ns ns 1 1 1 1 Output hold from address change t OH Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z t CLZ t OLZ t CHZ Output disable to output in high-Z t OHZ Note: 1. Transition is measured 200 mV from steady voltage with Load (B). This parameter is sampled and not 100% tested. 6 HM629127H Series Read Timing Waveform*3 t RC Address Valid address t AA t ACS t OH t CHZ CS t OE OE t OLZ t CLZ Dout High Impedance *1 t OHZ Valid data Note: 1. When CS and OE are low, Dout is low impedance. 7 HM629127H Series Write Cycle*1 HM629127H -20 Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Symbol Min t WC t AW t CW t WP t AS t WR t DW t DH 20 15 12 12 0 0 10 0 3 -- Max -- -- -- -- -- -- -- -- -- 7 -25 Min 25 20 12 12 0 0 10 0 3 -- Max -- -- -- -- -- -- -- -- -- 7 Unit ns ns ns ns ns ns ns ns ns ns 4 4 2 3 Notes Write disable to output in low-Z t OW Write enable to output in high-Z t WHZ Notes: 1. 2. 3. 4. A write occurs during the overlap of low CS, low WE. t AS is measured from the latest address transition to the later of CS or WE going low. t WR is measured from the earliest of CS or WE going high to the first address transition. Transition is measured 200 mV from high impedance state's voltage with Load (B). This parameter is sampled and not 100% tested. 8 HM629127H Series Write Timing Waveform (1) (WE Controlled) t WC Address Valid address t AW t AS WE *1 t WR t WP t CW CS t WHZ Dout t DW Din *2 t OW t DH *2 Valid data Notes: 1. WE must be high during address transition except when the device is disabled with CS. 2. If CS and OE are low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the outputs must not be applied to them. 9 HM629127H Series Write Timing Waveform (2) (CS Controlled) t WC Address Valid address t AW t WP WE t CW CS t AS t DW *1 t WR t DH Din Valid data Note: 1. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state. 10 HM629127H Series Low VCC Data Retention Characteristics (Ta = 0 to +70C) This characteristics is guaranteed only for L-version. Parameter VCC for data retention Symbol VDR Min 2.0 Typ -- Max -- Unit V Test Conditions VCC CS VCC - 0.2 V, VCC Vin VCC - 0.2 V or 0 V Vin 0.2 V Data retention current I CCDR -- 0 5 2 -- -- 80*1 -- -- A ns ms Chip deselect to data retention time t CDR Operation recovery time Note: 1. VCC = 3.0 V tR Low V CC Data Retention Timing Waveform t CDR V CC 4.5 V Data retention mode tR 2.2 V V DR CS 0V VCC > CS > VCC - 0.2 V 11 HM629127H Series Package Dimensions HM629127H Series (CP-36D) 23.25 23.62 Max 36 19 10.16 0.13 Unit: mm 1 3.50 0.26 0.74 18 2.85 0.12 1.30 Max 0.43 0.10 1.27 0.10 0.80 +0.25 -0.17 11.18 0.13 9.40 0.25 12 |
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